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ST's two- and four-channel unity-gain clock distribution circuits feature an individual clock-enable pin for each output. The devices driven by the clock outputs are isolated and interference between them is minimized. Each of the clock buffers can be disabled to lower the power consumption, optimizing battery life in handheld devices.
By distributing a single master clock to multiple clock domains, designers eliminate multiple individual clock sources for circuits supporting GSM, Bluetooth, WLAN, WiMAX or other RF communications, as well as in set-top-box applications.
| Part Number | General Description | Package | Marketing Status |
| STCD1040 | Clock Distribution Circuit | DFN12 2X3X0.75 | NRND |
| STCD2400 | Multichannel clock distribution circuit | Flip-Chip 400u | NRND |
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